Integrated circuit devices that provide a large plurality of multiple CCD gate structures are in common use today. By way of example, virtually all modern video cameras use such devices. Multiple CCD gate structures are also in use for vector matrix multiplication such as the CCD/CID vector matrix multiplier disclosed in the applicant's previously filed patent application Ser. No. 07/534,250 filed on Jun. 7, 1990. They may also be used in charge domain analog-to-digital converters, such as that disclosed in the applicant's co-pending patent application Ser. No. 07/597,020 filed concurrently herewith. In all such known uses for multiple CCD gate structures, it is desirable that the potential well characteristics that dictate the storage of charge beneath each such CCD gate be identical among the various gates on a chip. Unfortunately, even slight manufacturing variations from gate to gate on a single chip produce differences in each gate's potential and although these differences may only be equivalent to about a few millivolts, even such small differences can create inaccuracies and computational errors which detract from the otherwise significant advantages of CCD devices.
It is well known in the electronics art to use an ultra-violet light-activated floating gate for digital storage, such as in UV EPROMS. The binary storage provided by the read only memory may be altered by applying a digital value such as a 1 or 0, to each location within the programmable read only memory device, but only when an ultra-violet light is applied to the device or when extremely high electric fields are applied. During the application of UV light, the electrons in the insulator surrounding the floating storage gate are excited into the conduction band to permit current flow therein and hence modify the floating storage gate's potential. While the use of ultra-violet light activation of floating gates for digital storage is well known, it is believed that it has never been applied to CCD's, such as for the purpose of programming each gate of a multiple gate CCD structure in order to compensate for the fixed voltage bias of each such gate inherent to the manufacturing process.
It is believed that some relevant prior art work has been done at the Massachusetts Institute of Technology by John Sage and Alice Chiang, on the use of MNOS CCD structures where an outside surface is used to store an adjustable charge which can compensate for variations in CCD gate voltage biases. Unfortunately, this prior art process requires a special oxide coating which is relatively non-standard in the electronics industry and which therefore requires special machinery at increased cost and manufacturing complexity.
There is therefore a need to provide a more suitable and conventional means for controlling the fixed voltage bias in each gate of a CCD gate structure, which process may be incorporated in fabricating the CCD integrated circuit chip without adding any substantial cost thereto and wherein a relatively permanant voltage bias adjustment may be made to each individual CCD gate to compensate for manufacturing variations that would otherwise create differences in the inherent bias and therefore the potential well depth associated with each such gate.